The AD7569 contains an ADC and a DAC. The jumpers JP1 and JP2
are used to select the range and data format of both converters, according
to the next table.
<#835#>Table<#835#>:
<#836#>Selectable voltage ranges and data formats<#836#>
| JP1 (RANGE) |
JP2 (Vss) |
voltage range |
DB0-DB7 data format |
| 0 V |
0 V |
0 #math20#→ +1.25 V |
binary |
| 5 V |
0 V |
0 #math21#→ +2.5 V |
binary |
| 0 V |
-5 V |
-1.25 #math22#→ +1.25 V |
2s complement |
| 5 V |
-5 V |
-2.5 #math23#→ +2.5 V |
2s complement |
|
The inverted RESET of the XT bus is connected to the AD7569's
#math24##tex2html_wrap_inline839# input. The clock (CLK) is connected to an
RC circuit, enabling the conversion frequency to be adjusted with the
variable 10K resistor. A value of 6.8 kΩ corresponds to an
AD conversion time of #math25##tex2html_wrap_inline842# 2 μs. The analog input and output
voltage are connected to a 9-pin hooked SUB-D connector.